1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a flash memory device and a method for fabricating the same that reduces source line resistivity and a device chip size.
2. Background of the Related Art
FIG. 1A illustrates a plan view of a background art flash memory, and FIG. 1B illustrates a cross section along line I--I in the device of FIG. 1A. Referring to FIGS. 1A and 1B, the background art flash memory is provided with a plurality of tunnel oxide films 2 and floating gates 3 stacked over a semiconductor substrate 1. Gate oxide films 4, control lines 5 and gate cap insulating films 6 are formed extending along one direction to cover the floating gates 3. Source regions 7a are formed in the semiconductor substrate 1 along one side of the control gate lines 5 stacked over the floating gates 3. The source regions 7a are connected outside the flash memory device through one self-aligned source contact region 7.
Sidewall spacers 8 are formed on both sides of the tunnel oxide film 2, the floating gate 3, the gate oxide film 4, the control gate line 5 and the gate cap insulating film 6. However, the sidewall spacers 8 between the floating gates 3 above the source contact region 7 are further etched down to sides of the gate oxide films 4. Drain regions 9a are formed in the semiconductor substrate 1 on the other side of the control gate lines 5 stacked over the floating gates 3, and bit line contact regions 9 are formed to expose the drain regions 9a. Bit line wirings 10 in contact with the bit line contact regions 9 are disposed in a direction perpendicular to the control gate lines 5.
As described above, the background art flash memory has various problems. The source resistance difference of flash memory cells coming from different positions in the array causes non-uniformity in programming and read. In the case of the background art flash memory cell having an SAS process applied thereto, the source resistance difference varies between 100 ohms to 2000 ohms depending on the cell position in an array, which causes non-uniformity of a programming voltage and cell current in programming and reading. The unequal programing voltages and cell currents within the cell array that reduce efficiency of the programming and reading operations. Further, the exposure of the gate oxide film, an inter poly dielectric, to an etching ambient when spacers are formed at sides of the source contact region by an anisotropic etching can damage the gate oxide film. In addition, as a cell size is reduced, it is difficult to secure spaces between adjacent bit lines formed in the bit line contact portions on the drain regions. That is, layout tolerances for active regions and bit lines are decreased because the bit line contacts are disposed on a straight line.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.